A common memory element used in integrated circuits is referred to as a “flip-flop”. A flip-flop is a circuit that can maintain a binary state indefinitely (as long as power is applied to the integrated circuit) until directed by an input signal to switch states. The flip-flop switches can switch state in response to, for example, a rising edge of a clock signal (i.e., when the clock signal changes from 0 (low) to 1 (high) or vice-versa).
In general, the flip-flop stores a received data signal at the input terminal during a rising edge of a clock signal. In order for the stored data to be propagated to the output terminal of the flip-flop, the received data signal needs to be stabilized at the input terminal, referred to as setup time ‘ts’, before the clock signal is received at the flip-flop. Similarly, it is also necessary for the data signal to be stabilized at the input terminal for a further time period, referred to as ‘th’, after the clock signal is received. The sum of the setup and hold times ts and th defines a time period, referred to as a “constraint window” during which the data signal must be stabilized at either 0 or 1. For similar reasons, the data signal has to be stable during the constraint window for the flip-flop to capture and output the data signal to the output terminal. Therefore, the generated output data signal at the output terminal appears after a delay from a clock positive edge. This time delay is generally referred to as CLK-to-Q propagation delay of the flip-flop.
Generally, the setup time ts, hold time th, and CLK-to-Q propagation delay of a flip-flop vary depending on the flip-flop design. Also, setup time ts and hold time th can be negative depending on the design of the flip-flop. A typical implementation of the flip-flop can have a negative setup time, if it has a long route for a clock signal. The hold time th can be negative if it has a long route for a data signal. In either case, the sum of the setup time ts and hold time th will be positive.
Typically, digital circuits are verified for desired operation by performing a logic simulation using a hardware description language (HDL), such as Verilog or a Very high speed integrated circuit hardware description language (VHDL). The logic simulators simulate a digital circuit by creating events in time for every change in the logic value of nodes in the digital circuit. For expected simulation results, generally the events have to be evaluated in a proper sequence.
In such situations, logic simulators implement a negative constraint calculation (NCC) using an NCC algorithm to overcome the simulation inaccuracy when simulating elements having negative constraints. The current NCC algorithms simulate the original layout route delays by adding delay elements to the data and clock input terminals D and CLK. However, if the applied CLK-to-Q propagation delay is less than the delay applied to the input clock signal, i.e., having a negative setup time ts of magnitude greater than CLK-to-Q propagation delay, then the adjusted CLK-to-Q propagation delay can be negative. The negative CLK-to-Q propagation delay means that the outputted data signal appears before the input data signal occurs. Since this cannot be simulated, the NCC algorithm zeros out the CLK-to-Q propagation delay. When the NCC algorithm zeros out the CLK-to-Q propagation delay the simulated path delay will be set to “ts” (which is the delay applied onto the input clock signal), and hence results in an inaccurate CLK-to-Q propagation delay. In such conditions, the NCC algorithm fails to adjust negative constraints as expected. This can result in larger path delays and which can in-turn result in affecting the timing accuracy during an event driven simulation of a digital logic circuit.